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Monday, May 13


Registration & Breakfast / 签到和早餐

Monday May 13, 2019 08:30 - 09:00
Bund Ballroom Foyer 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Introduction to RISC-V / RISC-V 简介

Monday May 13, 2019 09:00 - 09:20
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Nuclei RISC-V Solution Paves the Way to Your Application Defined Chip / Nuclei RISC-V解决方案为您的应用定义芯片铺平了道路
Nuclei System Technology Co. Ltd. is a leading RISC-V core IP company in China. We focus on popularization and commercialization of RISC-V and work with our partner and the local community to grow the ecosystem in China. Bob Hu, the founder of the company, is a famous RISC-V technology evangelist. He is the creator open source RISC-V core Hummingbird E203, and the author of the first and the second RISC-V books in Chinese. Together with him, we continuously share our passion and thought of RISC-V to the others. Happily, more and more people not just only know what is RISC-V and start to adopt the cores based on it in their product. Currently, we have released N200 series ultra-low power RISC-V core IP for IoT application and is actively extending the product line. Our vision is to work closely with partners to help our customers to reach success by accelerating the innovation. In this talk, we will introduce how Nuclei RISC-V solution can pave the way to your application defined chip.

芯来科技有限公司是中国领先的 RISC-V 内核 IP 公司,专注于推动 RISC-V 的普及和商业化,携手合作伙伴与本地社区拓展中国的 RISC-V 生态系统。公司创始人胡振波是知名的 RISC-V 技术领袖,创建了开源 RISC-V 内核蜂鸟 E203,并撰写了中国第一本和第二本 RISC-V 专著。在他的带领下,我们锲而不舍,满怀激情地向他人宣传 RISC-V 的优势和光明前景。令人欣喜的是,越来越多的人不仅知道了 RISC-V 是什么,而且开始在他们的产品中采用内核。目前,我们已经发布了面向物联网应用的 N200 系列超低功耗 RISC-V 内核 IP,并正在积极扩展产品线。我们的愿景是与合作伙伴密切协作,加快创新步伐,帮助客户抵达成功的彼岸。在今天的演讲中,我们将介绍芯来 RISC-V 解决方案如何为您的应用定义芯片铺平道路。


Bob Hu

Nuclei System / 芯来科技
Bob Hu is the founder of Nuclei system technology, and the creator of first open source RISC-V core in China. He is the author of the first and second RISC-V books in Chinese. He has more than 8 years CPU and 10 years ASIC engineering experience. He was ARC processor R&D manager of... Read More →

Monday May 13, 2019 09:20 - 09:40
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Pushing data from the edge to the cloud with RISC-V ecosystem / 利用 RISC-V 生态系统将数据从边缘推向云端
Alibaba Group will deeply participate in the improvement and enrichment of the risc-v ecosystem, and promote the infrastructure construction of the IoT era based on the risc-v architecture.

阿里巴巴集团将深度参与 RISC-V 生态系统的建设,促进其改进和完善,推动基于 RISC-V 架构的基础设施搭建,为企业迈入物联网时代铺平道路 。


Caffrey Chen

Alibaba / 阿里巴巴
Caffrey Chen Ph.D. in Engineering. Bachelor degree in Electronic Information Engineering, Master degree and Ph.D. degree in Circuit and System, Zhejiang University. Mainly engaged in embedded processor architecture design, and deeply studied in high-performance branch processing and... Read More →

Monday May 13, 2019 09:40 - 10:00
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Productivity tools for automated generation of RISC-V processors / 面向自动化一代 RISC-V 处理器的办公工具
The emergence of the RISC-V architecture has given rise to a demand for widely differing microarchitectural implementations, ranging from deeply embedded microcontrollers to DSPs to superscalar processors.

To meet the challenge of addressing so many different operating points it is necessary to abstract the architectural details and to automate the generation and verification of RISC-V processors.

The Codasip approach to delivering RISC-V processor IP is to employ the silicon-proven methodology of the high-level CodAL architecture description language and its suite of tools called Codasip Studio™ to implement various RISC-V microarchitectures

Using Codasip Studio (an Eclipse-based integrated processor development environment) designers write a high-level description (in CodAL architecture description language) of a processor and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip has made various enhancements in order to optimize Codasip Studio and the CodAL language for the generation of RISC-V processors. The recently launched the 7th generation of Codasip Studio adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs.

Typical use cases for Codasip Studio are processor prototyping for a specific application domain, fast design space exploration, or development of custom extensions using Codasip’s architecture description CodAL language. In the last use case Codasip Studio generates hardware and corresponding SDKs that are aware of the custom extensions, including
• Readable Verilog or VHDL RTL and System Verilog UVM environments,
• testbenches and synthesis scripts,
• SDK consisting of LLVM based compiler, advanced profiling and debugging tools,
• both cycle-accurate and fast instruction-accurate simulation tools.

Codasip engineers have used the Codasip Studio design flow to create the broadest portfolio of RISC-V processors in the industry, and they now put the power in the hands of customers to further customize and extend the RISC-V instruction set, based on the unique requirements of the algorithms being run.

The presentation, among the other things, will cover the following new functionality:

• Improvements to SIMD support for up to 1024 bit.
• Native support for industry-standard AMBA interfaces, allowing for easy replacement of other processor cores while reusing your existing, proven peripheral IP.
• IEEE 1149-7-compatible 2-wire JTAG to minimize pin-count.
•        Major updates to software tools, including support for LLVM 6


Tina Xiang

General Manager / 总经理, Codasip
Graduated from Shanghai Tongji University with master degree in Circuit and System design domain. Worked in Hisilicon Terminal chips department for more than 6 years. Worked in Shanghai Jiatao as sales manager for a couple of years. Now is the general manager of Codasip China... Read More →

Monday May 13, 2019 10:00 - 10:20
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Morning Break / 上午茶歇
Monday May 13, 2019 10:20 - 10:50
Bund Ballroom Foyer 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


How to choose your AIoT RISC-V core? / 如何选择你的AIoT RISC-V核心?
Along with a number of open-source and commercial RISC-V cores are booming on the market, this presentation provides you a selection guide of cores and long-term partners for AIoT processors and applications.

从使用者的角度解析众多的开源跟商用的RISC-V核心当中,要如何选择适合你应用跟策略伙伴的AIoT 处理器核心。

avatar for John Shih / 石佳弘

John Shih / 石佳弘

Deputy Director, Technical Service / 技术服务副总监, Andes Technology
2019– Present      Deputy Director, Solution Architecture Division at Andes Technology Corporation2017 – 2019         Manager, Marketing & Technical Service Division at Andes Technology Corporation2012 – 2017         Deputy Technical Manager, VLSI Deputy Technical... Read More →

Monday May 13, 2019 10:50 - 11:10
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Perf-V: The cost-effective development board for RISC-V community / Perf-V:面向 RISC-V 社区的高性价比开发板
We design the Perf-V Dev Board for RISC-V community. The Perf-V Dev Board equip with Xilinx Artix-7 FPGA, 256MB DDR3 memory, flash, and peripheral interfaces (including Arduino, PMOD, and high-speed interface). On Perf-V, we support various RISC-V cores, including two-stage pipeline HummingBird E200 and five-stage pipeline X-core. Upon RISC-V cores, we provide embedded applications and experiments, e.g. smart car, drone, and etc. Meanwhile, RISC-V application developers could use Perf-V IDE (Eclipse with the plugin) to compile and debug the source code on the Perf-V board. Additionally, we provide the reference documents and slides for teaching computer organization course, and embedded system course on RISC-V ISA. Therefore, the Perf-V Dev Board fulfills the need of RISC-V geeks, students, and teachers in universities.

我们专为 RISC-V 社区设计了 Perf-V 开发板。Perf-V 开发板配有 Xilinx Artix-7 FPGA、256MB DDR3 内存、闪存和外设(包括 Arduino、PMOD 和高速接口)。Perf-V 支持各种 RISC-V 内核,包括 2 流水蜂鸟 E200 和 5 流水 X 内核。我们利用 RISC-V 内核实施智能汽车、无人机等方面的嵌入式应用和实验。同时,RISC-V 应用开发人员可使用 Perf-V IDE(Eclipse 具有该插件)在 Perf-V 开发板上编译和调试源代码。此外,我们还提供用于讲授计算机组织课程和嵌入式系统课程(RISC-V ISA 专题)的参考文档和幻灯片。因此,Perf-V 开发板可全面满足 RISC-V 极客、学生和大学教师的需求。


先轶 张

CEO, PerfXLab澎峰科技
PerfXLab cofounder, OpenBLAS project maintainer.澎峰科技联合创始人,OpenBLAS 项目维护负责人。

Monday May 13, 2019 11:10 - 11:30
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Enabling AIoT with RISC-V on a battery for years / 使用 RISC-V 打造依赖电池长期运行的 AIoT
2018 is a year of AI, people starts to look at how to make "AI IN ALL" becomes true. Running AI on a battery for years seems impossible? GreenWaves will present you how they realize this with their Extended RISC-V based AIoT application processor -- GAP8

2018 年是人工智能加速发展的一年,人们开始努力将“人工智能融入大千世界”(AI IN ALL) 的愿景转变为现实。依赖电池长期运行的人工智能技术似乎根本不可能实现?GreenWaves 将向您演示基于扩展 RISC-V 的 AIoT 应用处理器 (GAP8) 如何将不可能化为可能。


Zhang Yao / 张垚

Yao ZHANG, Lead Software Engineer at GreenWaves Technologies, who is one of the key contributor of Greenwaves' software (SDK, tools and OS), customer support and business development. Great enthusiasm in new technologies, espacially in RISC-V, processor achitecture, and AI applications.张垚目前担任 GreenWaves... Read More →

Monday May 13, 2019 11:30 - 11:50
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Lunch / 午餐
Monday May 13, 2019 11:50 - 13:00
Bund Ballroom Foyer 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


SCRx family of the RISC-V compatible processor IP / 兼容 RISC-V 的处理器 IP 的 SCRx 系列
We present family of the state-of-the-art RISC-V compatible microprocessor core IP developed by Syntacore: from the compact MCU core for the deeply-embedded applications to the 1GHz+ Linux-capable application cores with full MMU, memory coherency and multicore configurations support. With the recently announced additions, SCRx family now includes eight off-the-shelf cores, targeted at different applications: SCR1, SCR3, SCR4, SCR5 and SCR7 (SCR3, SCR4 and SCR5 can be instantiated as both 32bit and 64bit designs). Different cores can be deployed together in heterogeneous multicore clusters with atomics and memory coherency. The SCRx cores have competitive features and deliver impressive performance at low power already in the baseline configurations. On the top, Syntacore provides a one-stop workload-specific processor customization service to enable customer designs differentiation via significant performance and efficiency boost. Industry-standard interfacing options support (AHB, AXI4, ACE) enables seamless integration with existing designs. In the session, we detail cores features, benchmarks and collateral availability.

我们将介绍 Syntacore 开发的一系列兼容 RISC-V 的先进微处理器内核 IP,从面向深度嵌入式应用的紧凑型 MCU 内核到支持 Linux 的 1Ghz+ 应用内核等。它们具有全面的 MMU、内存一致性与多核配置支持。加上最近发布的新品,SCRx 系列现在包括面向不同应用的八款现成内核:SCR1、SCR3、SCR4、SCR5 和 SCR7(SCR3、SCR4 和 SCR5 均提供 32 位和 64 位两种设计)。不同内核可一起部署到异构多核集群中,并保持原子与内存一致性。SCRx 内核拥有极具竞争力的特性,能够在基准配置中以较低功耗实现卓越性能。Syntacore 还提供了一站式工作负载特定处理器定制服务,以大幅提升性能和效率,为客户创造差异化设计优势。行业标准接口选项支持(AHB、AXI4、ACE)可保障与现有设计的无缝集成。在这一课,我们将详细介绍内核特性、性能指标评测和附属产品等事宜。


Alexander Redkin

Executive Director, Syntacore
Alexander Redkin is Executive Director and co-founder at Syntacore. Prior to establishing Syntacore in 2015, Alexander had more than 15 years of experience in semiconductor industry in senior engineering and management roles, including more than 12 years at Intel R&D, where he contributed... Read More →

Monday May 13, 2019 13:00 - 13:20
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


RISC-V enters the mainstream - next steps for the ecosystem / RISC-V 进入主流市场 - 生态系统的下一步计划
In the beginning, the RISC-V story was about an instruction set architecture. Then, it was about CPU cores. Now, it's about building systems, and a healthy ecosystem. This presentation looks at progress so far in making RISC-V a commercial reality, and addresses some of the challenges for the future if RISC-V is to become even more successful. 

最初,RISC-V 只提供指令集架构,后来推出了 CPU 内核,现在开始专注于构建系统和打造健康的生态系统。本演示文稿回顾了 RISC-V 迄今为止的商业化进展,分析了 RISC-V 在未来前进道路上面临的一些挑战。


John Hartley

VP Global Sales, UltraSoC Technologies Ltd
John has over 25 years of experience in the semiconductor industry, and has previously held senior roles in both start-ups and prominent trans-national companies. Prior to joining UltraSoC, John held senior positions at Microchip, Tundra Semiconductor (now IDT) and PLX (now Broadcom... Read More →

Monday May 13, 2019 13:20 - 13:40
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


TG403: a high-performance secure RISC-V based MCU for embedded applications / TG403:专为嵌入式应用打造的基于 RISC-V 的安全高性能 MCU
TG403 is a new high-performance MCU product for embedded applications from Tangram Technologies, Inc. It has a RISC-V scalar core supporting RV32IMAFC with vector accelerator. The core employs a 6-stage dual issue pipeline running at least 500MHz clock frequency on TMSC 40nm ultra low power process. In this talk, we will discuss the most important features, design choices, and characteristics of TG403 for high performance and security protection purposes.

TG403 是一款面向嵌入式应用的全新高性能 MCU 产品,由 Tangram Technologies, Inc.倾力打造。该产品具有 RISC-V 标量内核,借助矢量加速器可支持 RV32IMAFC。该内核使用六级双指令 (dual issue) 管线,基于 TMSC 40 纳米超低功耗制程,运行时的最低时钟频率为 500MHz。在今天的演讲中,我们将讨论 TG403 的最重要特性、设计选择和特征,以及其出色的性能和安全保护功能。


Dai Donglai

Donglai Dai 博士目前担任 Tangram Technologies, Inc.的首席执行官,过去曾在英特尔公司、Cray Inc、Silicon Graphics Inc 等公司担任高级工程师、经理、高管等职位。他在物联网、VLSI、计算机系统和通信网络等领域拥有丰富经验和全面的专业知识。他是一位坚持“客户至上”理念的卓越领导者,习惯以身作则,推崇诚信、团队合作、持续学习等宝贵品质。他拥有俄亥俄州立大学计算机科学博士学位。Dr... Read More →

Monday May 13, 2019 13:40 - 14:00
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Afternoon Break / 下午茶歇
Monday May 13, 2019 14:00 - 14:30
Bund Ballroom Foyer 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Expanding RISC-V ecosystem for China Adoption / 扩展RISC-V生态系统,助力中国市场
  • NXP want to be with you at the forefront of this revolutionary technology and facilitate a deep RISC-V ecosystem . 
  • Introduce the hobbyist users website: open-isa. 
  • Introduce the free RISC-V boards: VEGAboard and VEGA-Lite 
  • Design contest with VEGA-Lite board 
  • Looking for cooperation with Universities and partners to expand the China RISC-V ecosystem together.

- 恩智浦期待与您携手推广这一革命性技术,建立庞大的 RISC-V 生态系统
- 推出发烧级用户网站:open-isa
- 推出免费 RISC-V 开发板:VEGAboard 和 VEGA-Lite
- 建立 VEGA-Lite 开发板设计大赛
- 期待与大学等合作伙伴携手前行,共同扩大中国的 RISC-V 生态系统

avatar for 万富(Richy) 叶

万富(Richy) 叶

Sr. MCU Systems Engineering Manager, NXP Semicondutors
System level applications for broad MCU products. Supporting new MCU products introduction and providing system level solutions for market promotion.

Monday May 13, 2019 14:30 - 14:50
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080


Innovation Unleashed: Solutions and Silicon Enabling the Intelligent Edge and Linux / 创新成果:支持智能边缘和 Linux 的解决方案和芯片

Thomas Xu

CEO, SiFive

Monday May 13, 2019 14:50 - 15:10
Bund Ballroom 上海外滩茂悦大酒店 / Hyatt on the Bund Shanghai, 199 Huang Pu Road Shanghai, China, 200080